Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In gate stacking, we proposed tri-layer HfO2/TiO2/HfO2 as high-K dielectric and hafnium zirconium oxide (HZO) ferroelectric (FE) layer. The GAA-TFET overcomes thermionic limitation (60 mV/decade) of conventional MOSFETs’ subthreshold swing (SS) thanks to its improved electrostatic control quantum mechanical tunneling. Simultaneously, NC state materials improves TFET performance by exploiting differential amplification voltage under certain conditions. most surprising discoveries this device, which outperforms all previous results, are very high $I_{ON}/I_{OFF}$ ratio order 1011 enormous on-state current 135 notation="LaTeX">$\mu \text{A}$ . incorporation effect with 9 nm HZO results in lowest SS 20.56 mV/dec (52.38% lower than baseline TFET) highest gain 6.58. Furthermore, output characteristics revealed large transconductance ( notation="LaTeX">$g_{m}$ ) 7.87 mS (103 higher TFET), drain-induced barrier lowering (DIBL) 9.7 mV, threshold 0.53 V (37.65% significant. Thus, indicate that device structure may lead new route for electronic devices, creating speed power consumption.